The present invention is directed to a digital logic circuit including a master-slave flip-flop with timing error correction, and to a method of operating a master-slave flip-flop with timing error correction.
Digital logic circuits such as data processors include sets of circuit elements forming logic “pipelines” through which digital signals propagate and are processed. The propagation of the digital signals from the output of each circuit element to the input of the following circuit element may be synchronized using clock signals. Signal propagation delays may occur either statically, due to manufacturing tolerances, or dynamically, due to variation in operating conditions such as supply voltage or temperature or noise, for example. If such delays cause the signal input to occur outside the correct clock phase, the timing error may cause malfunction of the digital logic circuit.
Master-slave flip-flops are widely used as circuit elements of digital logic circuits. Typically a master-slave flip-flop comprises two series connected gated latches driven by a two-phase clock signal. The master latch stores the value of the input signal at the trailing edge of a first phase of the clock signal, which is the active clock edge for the master latch. The slave latch stores the value of the output signal from the master latch at the trailing edge of the following, opposite phase of the clock signal, which is the active clock edge for the slave latch.
Timing errors in flip-flops may appear as meta-stability, when a data input changes too close to the active edge of the clock pulse. The result is that the output may become unpredictable, taking many times longer than normal to settle to its correct state, or even oscillating several times before settling. This can corrupt the data being processed. The meta-stability in a master-slave flip-flop can be reduced by ensuring that the data input to the master latch is held valid and constant for specified periods before and after the active edge of the clock pulse, called the setup time and the hold time respectively.
It is possible to reduce the likelihood of set-up time violations by detecting actual or potential timing errors and reducing the clock frequency. However, this may not be effective to reduce the likelihood of hold time violations. Thus, it would be advantageous to have a master-slave flip-flop that detects potential setup and hold time violations and corrects therefor.